1. Field of the Invention
The present invention generally relates to a method of manufacturing a semiconductor material layer, and more particularly, to a method of manufacturing a nano-crystalline silicon dot layer.
2. Description of Related Art
Memory devices derived from various semiconductor fabrication techniques such as dynamic random access memory (DRAM), static random access memory (SRAM), non-volatile random access memory (NVRAM) play a critical role in the semiconductor industry. With the gradual maturity of the processing techniques, these memories are widely adopted inside some of the popular electronic products including personal computers, mobile phones and networks.
However, as the size of newer generation of semiconductors continues to be miniaturized, of the size of the memories must also be correspondingly reduced, which is challenging. For example, the leakage current of a DRAM may lead to a large consumption of power, the area occupied by a SRAM may be too large and a higher voltage may be required to read/write flash memory data. Therefore, new types of memory devices having a higher density, lower memory volatility, faster read/write speed, unlimited access, low operating voltage, lower power consumption and compatibility with existing CMOS devices are highly demanded.
At present, among the newly developed memory devices, nano-dot non-volatile memory is more promising. Nano-dot non-volatile memory device is a memory device having a plurality of nano-dots formed in the charge storage layer such that each of the nano-dots may serve as an independent charge storage center. Thus, even if a leakage pathway is established within the tunneling oxide layer, the nano-dot non-volatile memory can still maintain a good charge retention capability. Moreover, as the size of the nano-dot memory is reduced, the nano-dot memory can still utilize its special properties to store charges inside the nano-crystalline dot layer and maximize the charge storage capacity of a memory storage device. Nowadays, research on silicon nano-crystalline dots, germanium nano-crystalline dots and metallic nano-dots progress at a fast pace because the nano-crystalline dot layers serving as a charge storage layers may replace the conventional silicon nitride charge storage layers.
A conventional method of forming a silicon nano-crystalline dot layer includes performing an ion implantation so that silicon is implanted into a silicon oxide layer and then performing a high-temperature annealing operation to crystallize the silicon into nano-crystalline dots. Another method of forming the nano-crystalline dot layer includes depositing crystalline silicon dots in particle form on a substrate in a low-pressure chemical vapor deposition process. Thereafter, silicon oxide is deposed to cover the crystalline silicon dots in a high-temperature oxidation (HTO) process so that the crystalline silicon dots are isolated from each other. However, the first method of using implanted silicon to form the crystalline silicon dots often leads to significant structural damage of the silicon oxide layer and causes insulation problems between crystalline silicon dots. The second method of performing a high-temperature oxidation process to form a silicon oxide layer over the crystalline silicon dots is difficult to completely cover all the crystalline silicon dots. Therefore, the insulation effect between the crystalline silicon dots is poor and ultimately may seriously affect the reliability of the device.